1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems, and in particular, to a method and system for computer simulation of digital devices, modules and systems utilizing a hardware description language (HDL) model. More particularly, the present invention relates to for improving a distributed simulation environment by reducing the size of data results transmitted and stored within the distributed simulation environment.
2. Description of the Related Art
Verifying the logical correctness of a digital design and debugging the design, if necessary, are very important steps in most digital design processes. Logic networks are tested either by actually building networks or by simulating networks on a computer. As logic networks become highly complex, it becomes necessary to simulate a design before the design is actually built. This is especially true when the design is implemented as an integrated circuit, since the fabrication of integrated circuits requires considerable time and correction of mistakes is quite costly. The goal of digital design simulation is the verification of the logical correctness of the design.
In a typical automated design process that is supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level description utilizing a hardware description language (HDL), such as VHDL, producing a representation of the various circuit blocks and their interconnections. The ECAD system compiles the design description into a format that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the design prior to developing a circuit layout.
A simulator is typically a software tool that operates on a digital representation, or simulation model of a circuit, and a list of input stimuli representing inputs of the digital system. A simulator generates a numerical representation of the response of the circuit, which may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general purpose computer or on another piece of electronic apparatus, typically attached to a general purpose computer, specially designed for simulation. Simulators that run entirely in software on a general purpose computer will hereinafter be referred to as “software simulators”. Simulators that are run with the assistance of specially designed electronic apparatus will hereinafter be referred to as “hardware simulators”.
Usually, software simulators perform a very large number of calculations and operate slowly from the user's point of view. In order to optimize performance, the format of the simulation model is designed for very efficient use by the simulator. Hardware simulators, by nature, require that the simulation model comprising the circuit description be communicated in a specially designed format. In either case, a translation from an HDL description to a simulation format, hereinafter referred to as a simulation executable model, is required.
As described in detail the above-referenced patent application, it is often the case that it is desirable for testing purposes to detect “instrumentation events,” which may occur over many cycles and may be composed of temporally complex interactions of a large number of signals within the given simulation model. In order to detect and quantify the occurrence of such instrumentation events, it is helpful to incorporate the necessary instrumentation logic and event counters within the simulation model so that the events of interest are detected and quantified directly by the simulation model.
As will be appreciated, in many cases, a particular portion of a digital design, hereinafter referred to as a “design entity,” is replicated numerous times throughout a circuit, module or system under simulation. Accordingly, the instrumentation logic needed to detect and quantify instrumentation events associated with the design entity is instantiated once for each instance of the design entity. This approach enables parties interested in the simulation results (e.g., simulation engineers) to associate particular instances of the design entity particular occurrences of an instrumentation event. This approach also creates enormous volumes of result data, particularly in distributed simulation environments in which numerous simulation models are being continuously exercised by a large number of simulation servers utilizing multiple test cases.
The present invention recognizes that as a practical matter, for some parties, some simulation models and/or some instrumentation events, it may not be interesting to know the particular instance of a design entity in which an instrumentation event was detected. Instead, it may be sufficient to know simply that the instrumentation event was detected, or at most, the aggregate number of a particular type of instrumentation event detected across all design entities within the simulation model. In such cases, the present invention recognizes that the size of the data results of the simulation can be advantageously reduced.